

module Adder
    #(
        parameter IWID=12,
        parameter OWID=32
    )
    (
        input wire signed [IWID-1:0] i_add1,
        input wire signed [IWID-1:0] i_add2,
        input wire i_clk,
        input wire i_rst,
        output reg signed [OWID-1:0] o_sum
    );

    wire signed [OWID-1:0] add_result;

    assign add_result=i_add1+i_add2;

    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            o_sum<='b0;
        end
        else begin
            o_sum<=add_result;
        end
    end

endmodule